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Draft specifications for a VME MCA and spectroscopy ADC
- Subject: Draft specifications for a VME MCA and spectroscopy ADC
- From: Mark Rivers <RIVERS@cars3.uchicago.edu>
- Date: Fri, 27 Jan 1995 15:19:00 -0600 (CST)
Folks,
I have drawn up the following draft specifcations for a VME multichannel
analyser and ADC which I would like to have built for use at the APS. I would
like to discuss this at the Feb. 23 meeting, and hope to get some feedback
before then.
I have begun preliminary discussions with a vendor who might be interested in
building a VME MCA system. Are there other CATs who would be willing to help
underwrite the development costs?
Mark Rivers
***************************************************************************
Draft Specifications for VME Multichannel Analyser System for use at the APS
Mark Rivers
January 27, 1995
The following are draft specification for a VME based MCA. The system is
assumed to consist of two modules: an MCA module with memory and timing control
and an ADC module. Each MCA module could support at least 4 ADC modules.
Multichannel Analyser Module
24 bit input from ADC
This allows:
2-D operation with 2 12 bit ADCs
Operation with 14 bit ADC and 10 tag bits
Acquisition modes
List mode - Store input value current channel location; increment channel
counter. This is used for 'event-mode' data acquisition and
SVA sampling mode on ADCs
Add 1 - Add 1 to channel referenced by input value. This is
conventional MCA histogramming
Add N - Add input value to current channel location; increment channel
counter. This is used with multichannel scalers.
Timing modes
Preset real time
Preset live time
Preset total counts in a range of channels.
Preset real time and live time range 1 msec - 10^6 seconds,
accurate to 10 usec or 0.01%.
In preset total mode, acquisition stops within 10 msec of reaching
preset total counts
Elapsed live time and real time available, accurate to within 10 usec or 0.01%.
32 data bits per channel (>4 billion counts/channel)
Minimum 1 MHz histogramming rate
Minimum of 1M channels (4 MB) capacity on board. Up to 16M channels with
companion memory boards.
Dual-ported memory with DMA to VME host
Capable of simultaneous operation from at least 4 ADCs. Common timing control
is acceptable.
Front panel indicators
Acquire - LED indicating that the module is enabled to acquire data
Active - LED indicating that data is being acquired from an ADC input
ADC
< 1 usec conversion time
13 bit (8192 channel) resolution
Input range 0 to +8V
Differential non-linearity: < +-1%
Integral non-linearity: < +-0.025%
Peak detect:
Automatic or delayed
Delay time programmable from 0.5 to 100 usec
Collection modes
Pulse height analysis (PHA) - Conversion on peak detect
Sampled voltage analysis (SVA) - Conversion on GATE pulse
Input signals
Input: Analog input, range 0 to +8V
Gate: TTL signal used for gating and coincidence
Programmable gain from 256, 512, 1024, 2048, 4096 channels full scale
Programmable lower-level discriminator (LLD), 12 bit resolution,
range 0V to +8V
Programmable upper-level discriminator (ULD), 12 bit resolution,
range 0V to +8V
Programmable coincidence modes:
Coincidence: High input on Gate or no input on Gate
Anticoincidence: Low input on Gate
The LLD and ULD are active during both PHA and SVA modes
Programmable zero offset voltage, 12 bit resolution, range +- 0.25V
Output signals:
Acquire: TTL level indicating that acquisition is enabled
Event: TTL pulse indicating that a conversion is complete
Data: A/D output on private 24 bit address bus to MCA board
Front panel indicators:
% dead time: LED bar graph
Active: LED indicating conversion in progress
Compatible with use with an analog multiplexor rather than direct amplifier
output. The analog multiplexor would present the voltage to the ADC input, and
manipulate the high order data bit to the MCA to indicate which amplifier a
pulse came from.